Analog-to-digital converters (ADCs) convert analog input signals into digital codes. One type of ADC is a successive approximation register (SAR) ADC. A SAR ADC essentially guesses a digital output code by successively comparing different digital codes with the input signal. To do this, a digital-to-analog converter (DAC) is used. The DAC is set to a particular value, and the analog output of the DAC is compared to the analog input signal. For example, in a 4-bit DAC, the DAC may be set to 1,0,0,0, which generates an analog signal at the midpoint of the range of the DAC. If the analog input signal is higher than this, the SAR keeps the ‘1’, and moves to the next bit. If the analog input signal is lower than this, is sets this bit to ‘0’. Assuming the analog input was higher than the digital signal, the SAR sets the DAC to 1,1,0,0, and performs the same comparison. Each of these comparisons is called a bit trial, and the process continues until the SAR settles on a digital code which is an approximation of the analog input.
When the input signal is slow moving, it is likely that the most significant bit (MSB) will not change between conversions. As such, to speed up the process, and to reduce power, the MSB can be preloaded. As such, rather than perform bit trials for all of the bits, bit trials are only performed for the latter bits. However, when the input signal moves towards the bit boundary, it becomes increasingly likely than the next digital output signal will not share the MSB. As such, if the MSB is preloaded based on the previous digital output, errors can occur.